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EM250
SC1_RATEEXP [0x44B2]
15
0-R
0
14
0-R
0
13
0-R
0
12
0-R
0
11
0-R
0
10
0-R
0
9
0-R
0
8
0-R
0
0
0
0
0
SC1_RATEEXP
0-R
7
0-R
6
0-R
5
0-R
4
0-RW
3
0-RW
2
0-RW
1
0-RW
0
NOTE: Changing the SC1_RATEEXP register is only allowed when the serial controller is
disabled, when SC1_MODE is 0.
SC1_RATEEXP
[3:0]
The exponential component (EXP) of the clock rate as seen in the equation: rate = 24MHz /
( 2 * (LIN + 1) * (2^EXP) )
SC1_SPICFG [0x44AC]
15
0-R
0
0
0-R
7
14
0-R
0
0
0-R
6
13
0-R
0
SC_SPIRXDRV
0-RW
5
12
0-R
0
SC_SPIMST
0-RW
4
11
0-R
0
SC_SPIRPT
0-RW
3
10
0-R
0
SC_SPIORD
0-RW
2
9
0-R
0
SC_SPIPHA
0-RW
1
8
0-R
0
SC_SPIPOL
0-RW
0
NOTE: Changing the SC1_SPICFG register is only allowed when the serial controller is
disabled, when SC1_MODE is 0.
SC_SPIRXDRV
SC_SPIMST
SC_SPIRPT
SC_SPIORD
SC_SPIPHA
SC_SPIPOL
[5]
[4]
[3]
[2]
[1]
[0]
Receiver-driven mode selection bit (SPI master mode only). Clearing this bit will initiate
transactions when transmit data is available. Setting this bit will initiate transactions when
the receive buffer (FIFO or DMA) has space.
This bit must always be set to put the SPI in master mode (slave mode is not valid).
This bit controls behavior on a transmit buffer underrun condition in slave mode. Clearing this
bit will send the BUSY token (0xFF) and setting this bit will repeat the last byte. Changing this
bit will only take effect when the transmit FIFO is empty and the transmit serializer is idle.
Clearing this bit will result in the Most Significant Bit being transmitted first while setting this
bit will result in the Least Significant Bit being transmitted first.
Clock phase configuration is selected with clearing this bit for sampling on the leading (first
edge) and setting this bit for sampling on second edge.
Clock polarity configuration is selected with clearing this bit for a rising leading edge and
setting this bit for a falling leading edge.
Page 51
120-0082-000V Rev 1.1
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